(1) Field of the Invention
The present invention relates to a device for converting an analog signal into a digital signal (A/D converter) of a parallel comparison type with error suppression circuits, a 2.sup.N-M number of M-bit encoders, and one N-bit encoder.
(2) Background of the Art
A parallel type or parallel comparison type analog-to-digital (A/D) converter having a superior high-speed operating characteristic is commonly used as the A/D converter.
An N-bit parallel type A/D converter generally includes 2.sup.N -1 numbers of comparison circuits disposed in parallel with each other and 2.sup.N numbers of serially connected resistors having mutually equal resistance values and across which a reference voltage (e.g., 2 volts is applied so as to provide an equal divided voltage across each resistor and to provide 2.sup.N -1 numbers of mutually different comparison voltages at terminals between the mutually adjacent resistors. Thus, each comparison voltage provided by the resistors is supplied to one of the input terminals of the corresponding comparison circuit and an input analog voltage is supplied to the other input terminal of each comparison circuit so that the comparison circuits detect which of these comparison circuits is nearest to the input analog voltage. Then, the A/D converter of the parallel comparison type encodes the detection result through a coincidence circuit to provide the N-bit digital signal indicating the digital value of the input analog voltage through the N-bit encoder.
If the number of bits of the above-described parallel A/D converter are, for example, eight bits (N=8), the numbers of resistors, comparison circuits, and gates in the coincidence circuitry reach 256 and the layout of the 8-bit A/D converter becomes very long when these circuit elements are aligned in a row.
That is to say, if such an 8-bit A/D converter is arranged on a single semiconductor chip in a rectangular shape, the layout thereof will be described below.
The 8-bit A/D converter described above is, e.g., divided into four blocks, each block being arranged in a unidirection and having a 6-bit encoder built therein. Then, an output signal of each 6-bit encoder is supplied to a single 8-bit encoder from which the 8-bit digital signal is outputted. Each block includes a comparator group, each group having 64 comparators. It is noted that each comparator includes a combination of one resistor, one comparison circuit, and one gate.
One comparator group belonging to one block is thus constituted by 64 comparators. Each number from 0 to 254 is sequentially allocated to all comparators of the A/D converter in an order from a lower significant number 0 to an upper significant number 255. It is noted that although the comparator in the order of 255 is present, it is not connected to the corresponding encoder.
Each 6-bit encoder is in a matrix form in which six bit lines are present for providing a 6-bit output signal thereat and a single block indicating line BDB is provided. The block indicating line BDB functions to inform the 8-bit encoder that a coincidence detection signal is transmitted from any one of the comparators or a particular comparator to the 6-bit encoder itself in the corresponding block to which the 6-bit encoder belongs.
Error suppression circuits are connected between respective blocks and the 8-bit encoder for preventing occurrence of errors by inhibiting the output of the signal from the 6-bit encoder connected to the corresponding error suppression circuit to the 8-bit encoder upon receipt of an output inhibit signal. The output inhibit signal is transmitted in a sequence from the highest error suppression circuit connected to the uppermost order block to the lowest order error suppression circuit connected to the lowest order block.
The details of one of the previously proposed parallel type A/D converters with the error suppression circuits will be described below.
In each 6-bit encoder of the blocks in the matrix construction, seven signals transmitted via the 6-bit bit lines and block indicating line BDB are inputted to the 8-bit encoder via a latch circuit and the corresponding error suppression circuit.
Allseven signals passed through the latch circuit are also inputted to an OR gate circuit. An output signal of the OR gate circuit is then transmitted to the adjacent lower order error suppression circuit as the output inhibit signal. Hence, each of the error suppression circuits receives the output inhibit signal from its adjacent, one upper-order block.
The above-described block indicating line BDB is connected to output terminals of all comparators of each comparator group connected to the 6-bit encoder of the corresponding group.
The error suppression circuits are provided for preventing a transient occurrence of a large error of such an order as indicated by 2.sup.6.
The transient occurrence of such a large error will specifically be described below.
For example, when the input analog voltage is changed in such a way as initially from a value slightly smaller than the value of 2 such as a (reference voltage).times.192/256, intersecting this value, and exceeding this value to a larger value, one of the comparators generating the output signal is changed sequentially in such a way that the output signal is generated from the comparator of the second block in the order of 65, the output signal is generated from the comparator of the second block in the order of 64, the output signal is generated from the comparator of the first block in the order of 63, and the output signal is thereafter generated from the comparator in the order of 62.
Although the block indicating signal BDB is outputted from the block indicating line of the second 6-bit encoder until the output signal from the comparator of the order of 64 is generated, the block indicating signal vanishes, which has been outputted via the block indicating line BDB of the second 6-bit encoder, when the comparator in the order of 63 generates the output signal. The change of the output bit status in the 8-bit encoder, i.e., the A/D converter is shown as follows during this period.
______________________________________ 01000001 .rarw. 9.sub.65 01000000 .rarw. 9.sub.64 00111111 .rarw. 9.sub.63 00111110 .rarw. 9.sub.62 ______________________________________
It is noted that in this case, the digital output when the output signal is generated from the comparator in the first order of 0 indicates 00000000 and that when generated from the comparator in the last order of 254 indicates 11111111.
However, the above-described change of the output digital signal is a case where each circuit element is ideally operated without delay. The operating speed of each circuit element is actually different for different circuit elements.
For example, if a delay of operation occurs in the second 6-bit encoder, a transient state often occurs such that the block indicating signal of the second 6-bit encoder does not vanish but remains 1 although the six bits of the first 6-bit encoder have already indicated 111111 when 01000000 is changed to 00111111.
In this case, the digital output signal is changed in the way described below.
______________________________________ 01000000 01111111 00111111 ______________________________________
In other words, the output signal indicating 01111111 often or seldom appears when changing from 01000000 to 00111111, although this phenomenon is transient.
This is a large indication error of the output signal since it is different from such an error as occurring in the output digit of a least significant bit (LSB) or near thereto.
To cope with such a transient error phenomenon, the error suppression circuits for the respective blocks are installed in the A/D converter.
Hence, e.g., when the output signal is generated from the second 6-bit encoder, the output inhibit signal is transmitted from the second 6-bit encoder to the first-order error suppression circuit. At this time, if the first line of the six bit lines of the first 6-bit encoder is generated, the input of the output signal therefrom to the 8-bit encoder is interrupted by this output inhibit signal. Hence, no large error occurs in the A/D converter described above.
However, the above-described previously proposed parallel type A/D converter has a drawback such very large numbers of elements such as transistors in the A/D converter.
That is to say, output lines of the comparators are connected to the 6-bit encoder in the matrix construction belonging to the same block and each 6-bit encoder is connected to each input line connected to the 8-bit encoder via transistors (or diodes), respectively. As the number of the connection points are increased, the number of transistors (or diodes) to be used is accordingly increased. Therefore, if the block indicating line BDB of the corresponding 6-bit encoder is connected to all comparators of the group, the number of the connection points requires 64 per block due to the connection of the output lines of the comparators to the block indicating lines.
This does not only result in an increase of the number of elements but also in a heavy load on each block indicating line. Consequently, the high speed operating characteristic inherent to the parallel type A/D converter deteriorates.
In addition, since the output inhibit signal to be transmitted to one of the error suppression circuits in one lower order is formed by passing the seven signals transmitted via the 6-bit bit lines and block indicating line through the OR gate circuit 12, the number of input terminals to the OR gate circuit therefore reaches seven. This is also a factor for increasing the number of circuit elements, such as transistors.
Since the number of transistors per input terminal in the OR gate circuit are greater, as many as 1 to 3, 7 to 21 transistors must be used in the signal inputting portion of the single OR gate circuit. When the input signal is transmitted through the OR gate circuit, its output inhibit signal is delayed. This makes the A/D converter disadvantageous.
In the manner described above, the previously proposed parallel type A/D converter has problems of such as the large number of circuit elements used therein and of providing unfavorable effects on the high-speed operating characteristic inherent to the A/D converter of the parallel comparison type.